ABDULLAH SAHRURI

Lafayette, LA 70506
abdullah.sahruri1@louisiana.edu
abdullah.sahruri@gmail.com

Summary

I am a PhD student in Computer Engineering at the University of Louisiana at Lafayette, where I work as a Graduate Research Assistant in analog and digital IC design. I have an MS in Electrical and Electronics Engineering from Yeditepe University, where I was an honor student and a Graduate Research Assistant.

I have multiple skills and experience in field-programmable gate arrays (FPGA), Verilog, AWR Microwave Office, and analog/digital IC projects for industrial applications. I am always looking for exciting work environments and new technologies, and I am interested in opportunities to expand my knowledge and experience of VLSI. My goal is to contribute to advancing nanoscale chip technology and create innovative solutions for real-world problems.

EDUCATION

University of Louisiana at Lafayette – Lafayette, LA
Ph.D. Computer Engineering (CGPA: 3.85) – 2023 - (Expected Grad. 2026)
Academic advisor: Martin Margala
Relevant Coursework: Analog VLSI Design • VLSI Structures • Computer Arithmetics • VLSI Testing
Design and Analysis of Algorithms • Principles of Computer Architecture • Computer Design and
Implementation • Principles of Programming Languages

Yeditepe University – Istanbul, Turkey
M.S. Electrical and Electronics Engineering (CGPA: 3.93) – 2019 - 2022
Thesis: High Fan-in Differential Capacitive-Threshold-Logic Implementation With an Offset-Compensated Comparator:
Designed a novel high fan-in threshold logic gate for fast data-intensive computations using capacitive feedback loops, MOSFET capacitors, and digital logic levels. Analyzed designs with 65nm CMOS technology.
Academic advisor: Ugur Cilingiroglu
Relevant Coursework: Analog IC Design • RF Circuit Design • Advanced Electronics • Sensors • Advanced Communication Systems • Advanced Control Systems • Advanced Robotic Systems

Yeditepe University – Istanbul, Turkey
B.S. Electrical and Electronics Engineering (CGPA: 3.25) – 2014 - 2019
Graduation Project: Lead-compensated Miller OTA as a unity-gain buffer amplifier using 90nm CMOS technology.
Simulated in Cadence Virtuoso, achieving a phase margin of no less than 65º and a settling time of 34 ns.
Academic advisor: Ugur Cilingiroglu
Relevant Coursework: Analog IC Design • High-Frequency Electronics • Physical Design Of IC • Digital IC Design • Analog Electronic Circuits • Microprocessor Systems • Coding And Information Theory • Wireless Communication • Antennas and Propagation

TECHNICAL SKILLS

Programming:
C • TCL • Python • Linux • HDL (Verilog, VerilogA, SystemVerilog, VHDL) • MATLAB

Computer-Aided Design:
Cadence Virtuoso • SKILL • Liberate • Cadence AWR • SPICE • HSPICE • Spectre

WORK EXPERIENCE

Memory Circuit Design Intern – Broadcom, Austin, TX
Full-Time Internship (May 2024 - August 2024)

Conducted latch characterization across process corners in advanced node technologies
Developed TCL scripts for layout placement, improving design efficiency
Created a Python-based design flow for automation and validation

Research Assistant – University of Louisiana at Lafayette, Lafayette, LA
Full-Time (2023 - Present)

Research in Hardware Security and VLSI Testing
Created circuits and layouts in Cadence Virtuoso for publications

PUBLICATIONS

A. G. Ayar, A. Sahruri, S. Aygun, M. S. Moghadam, M. H. Najafi, M. Margala, “Detecting Vulnerability in Hardware Description Languages: Opcode Language Processing,” IEEE Embedded Systems Letters, doi: 10.1109/LES.2023.3334728

A. Sahruri, M. Margala, U. Cilingiroglu. “HiCTL: High Fan-in Differential Capacitive-Threshold-Logic Gate Implementation With An Offset-Compensated Comparator”. 25th International Symposium on Quality Electronic Design (ISQED), San Francisco, CA, USA, 2024. doi: 10.1109/ISQED60706.2024.10528704

POSTER PRESENTATIONS

16th Dallas Circuits and Systems Society (DCAS)
Best Poster Award (April 2023)
“High Fan-in Differential Capacitive-Threshold-Logic Implementation With an Offset-Compensated Comparator”

IBM IEEE CAS/EDS – AI Compute Symposium (November 2023)
“A 32-bit Neuromorphic ALU Based on Threshold Logic Gates” – IBM T.J. Watson Research Center, Yorktown Heights, NY

PROFESSIONAL MEMBERSHIPS

Institute of Electrical and Electronics Engineers (IEEE)
Reviewer of ISCAS in the following tracks:

Design and Verification of Digital Integrated Circuits and Systems
Electronic Design Automation and Physical Design
Low-Power Logic Circuits and Architectures

Association for Computing Machinery (ACM)